1. Field of the Invention
The present invention relates to a memory system, and more particularly, a memory system and a memory management method including the same that reduce the number of memories therein.
2. Discussion of the Related Art
As the world is moving into the mobile multi-media era, portable multi-media devices incorporate more micro-processors and need larger and faster memory capacity to handle the multi-media data while maintaining the compactness of the devices. For example, a multi-media system may include two or more micro-processors, such as an application processor and a modem.
In general, each micro-processor requires its own non-volatile memories for holding its respective program codes and data, e.g., boot codes, such that program codes and data are not lost when the power supply is unavailable. In addition, each micro-processor requires additional memories for providing processing memory spaces. Such processing memories typically are volatile memories to reduce the manufacture cost.
Thus, the multi-media system generally includes one non-volatile memory and one volatile memory for each micro-processor in the system. In particular, as the number of micro-processors increases, the number of the memories also increases, thereby requiring more platform area and higher power consumption.
FIG. 7 is a schematic diagram illustrating a multi-processor system according to the related art. As shown in FIG. 7, a multi-processor system includes at least two processors, such as an application processor (“AP”) 1 and a modem processor (“MODEM”) 2. Each of the application processor 1 and the modem processor 2 requires a non-volatile memory for holding its respective management information.
In particular, the modem processor 2 is directly connected to a first flash memory 3. In addition, the modem processor 2 is connected to a first volatile memory 4. Further, the application processor 1 is directly connected to a second volatile memory 5 and is connected to a second flash memory 6. The first and second volatile memories 4 and 5 respectively provide processing memory spaces for the application processor 1 and the modem processor 2, and may be one of a mobile DRAM (“MDRAM”) and a random-accessible DRAM, such as UtRAM™. The first and second flash memories 3 and 6 respectively hold program codes and data for the application processor 1 and the modem processor 2, and may be one of a NOR flash memory, a NAND flash memory and an OneNAND™ flash memory, which takes advantages from high-speed data read function of a NOR flash memory and the advanced data storage function of a NAND flash memory.
FIG. 8 is a schematic diagram illustrating another multi-processor system according to the related art, and FIG. 9 is a schematic diagram illustrating the dual-port memory shown in FIG. 8. As shown in FIG. 8, each of the application processor 1 and the modem processor 2 requires a non-volatile memory for holding its respective program codes and data, e.g., boot codes. In addition, the application processor 1 and the modem processor 2 share a conventional dual-port volatile memory 7, such as a dual-port RAM memory.
As shown in FIG. 9, the conventional dual-port volatile memory has a first port PORT1 and a second port PORT2, which may respectively be connected to external devices, such as the application processor 1 and the modem processor 2 (shown in FIG. 15). Memory cells of the dual-port volatile memory 7 are accessible via both the first port PORT1 and the second port PORT2 simultaneously. For example, if a first memory address signal received via the first port PORT1 and a second memory address signal received via the second port PORT2 are the same, that is, if the external devices request to access the same memory cell of the dual-port memory, access collision would occur.